ASIC/SoC Functional Design Verification

Cracking Digital VLSI Verification Interview: Interview Success

Logic Design and Verification Using SystemVerilog (Revised)

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology

Verilog by Example: A Concise Introduction for FPGA Design

SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications

Digital Logic RTL & Verilog Interview Questions

Formal Verification: An Essential Toolkit for Modern VLSI Design